Importance

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Abstract

A system for providing a non-integer division of a single clock signal in a communication device, the communication device including at least two modules is provided. In a system aspect, the system includes first and second divider circuits within one module of the at least two modules, the first and second divider circuits dividing the single clock signal to produce a first clock signal and a second clock signal. The system further includes logic means within the one module and coupled to the first and second divider circuits, the logic means logically combining the first and second clock signals to produce a non-integer division of the single clock signal for use by the other module of the at least two modules.

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First Claim