Universal duty cycle adjustment circuit
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United States of America Patent
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-
Sep 19, 2000
Grant Date -
N/A
app pub date -
Oct 8, 1998
filing date -
Oct 8, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A duty cycle control circuit that consumes lower power and smaller silicon area, and is less susceptible to noise or jitter. In one embodiment, the invention includes a divide-by-two circuit that is edge triggered and generates a signal at its output with half the frequency of the input signal but with a 50% duty cycle. The divide-by-two circuit is followed by a frequency restore circuit that restores the original frequency of the input signal but with its duty cycle regulated at about 50%, or any other desired level.
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