System for optimizing the equalization pulse of a read sense amplifier for a simultaneous operation flash memory device
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United States of America Patent
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Sep 26, 2000
Grant Date -
N/A
app pub date -
Oct 19, 1999
filing date -
Oct 19, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A system for optimizing the equalization pulse of a read sense amplifier is disclosed. A number of capacitor circuits are provided that can be coupled to a timing circuit in a variety of combinations. The different combinations of coupled and decoupled capacitor circuits result in different durational lengths of the equalization pulse. A testing sequence determines the optimal durational length of the equalization pulse by testing the different combinations of coupled capacitors. The optimal combination is then permanently stored in attribute cells for optimizing the equalization pulse in normal operation.
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