Bus system, printed circuit board, signal transmission line, series circuit and memory module
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United States of America Patent
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-
Sep 26, 2000
Grant Date -
N/A
app pub date -
Jun 13, 1997
filing date -
Jun 13, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.
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