Importance

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Abstract

The programmable impedance circuit of the present invention includes a dummy resistance element dummy buffer means including a plurality of buffer portions, each buffer portion having a serial circuit made of a transistor and a resistance element, a binary selection signal generating circuit, connected to the dummy resistance element and the dummy buffer means, for controlling a current flowing in the dummy resistance element and a current flowing in a predetermined buffer portion of the dummy buffer to be equalized to each other, and outputting binary selection signals of a logic level corresponding to that it is regarded that matching of impedances before being input to an output buffer is achieved when both the currents are equalized to each other, and output buffer means for suppressing a variance of the impedance value even when an output voltage is in a transiently changing state, in accordance with the logic level of the binary selection signal as receiving binary selection signals from the binary selection signal generating circuit, and with complimentary logic levels as receiving complimentary input data.

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First Claim