Integrated wafer fab time standard (machine tact) database

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United States of America Patent

PATENT NO 6128588
SERIAL NO

08941831

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Abstract

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An integrated wafer fab production characterization and scheduling system incorporates a manufacturing execution system with a scheduling system based on simulation. The integrated characterization/scheduling system provides manufacturing with a simulation tool integrated with the manufacturing execution system to evaluate proposed production control logic as a practical alternative to expensive experimentation on actual production system. Furthermore, simulation models are used to create short term dispatch schedules to steer daily manufacturing operations towards planned performance goals. Innovative features include integration of preventive maintenance scheduling, Kanban based WIP control, an integrated time standard database, a, and real time lot move updates.

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Patent Owner(s)

Patent OwnerAddress
SONY CORPORATION7-35 KITASHINAGAWA 6-CHOME SHINAGAWA-KU TOKYO
SONY ELECTRONICS INC1 SONY DRIVE PARK RIDGE NJ 07656

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chacon, Guillermo Rudolfo San Antonio, TX 3 185

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