Continuously powered mainstore for large memory subsystems
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United States of America Patent
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Oct 3, 2000
Grant Date -
N/A
app pub date -
Aug 26, 1997
filing date -
Aug 26, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A memory arrangement, where a memory control logic, which drives a memory array, is maintained in a volatile power domain, and clock redrive circuitry, address control redrive circuitry, data transceiver, and the memory array itself are all maintained in a non-volatile power domain, in order to increase the effective life time of a battery backup system. The memory arrangement includes buffering circuitry to prevent leakage currents, and the appropriate control of nets between the memory control logic and the memory array, in order to avoid additional sources of leakage current and bus driver contentions.
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