Method of encapsulating a microelectronic assembly utilizing a barrier

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United States of America Patent

PATENT NO 6130116
SERIAL NO

08984933

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Abstract

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A method of encapsulating a microelectronic assembly includes providing one or more microelectronic assemblies having one or more elements defining exterior surfaces and an array of terminals exposed at the exterior surfaces, the one or more elements defining one or more apertures through the exterior surfaces. A layer of a curable barrier material is then provided on a supporting element. The barrier layer has openings therein in a pattern corresponding to the array of terminals on the one or more microelectronic assemblies. The supporting element and the one or more microelectronic elements are then assembled together so that the layer of barrier material contacts the exterior surfaces and covers the apertures and so that the openings in the layer of barrier material are aligned with the terminals. The barrier material is then cured while in contact with the exterior surfaces to thereby form a barrier layer covering the apertures. Next, a curable liquid encapsulant is applied to the microelectronic assemblies, whereby the barrier layer prevents the curable liquid encapsulant from flowing through the apertures, and the encapsulant is cured. The barrier layer and the supporting element cooperatively surround the terminals exposed at the exterior surfaces to protect the terminals from contaminants.

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Patent Owner(s)

Patent OwnerAddress
TESSERA INC3025 ORCHARD PARKWAY SAN JOSE CA 95134

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fjelstad, Joseph Sunnyvale, CA 130 7144
Smith, John W Palo Alto, CA 213 9165

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