Synthesis-friendly FPGA architecture with variable length and variable timing interconnect
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United States of America Patent
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Oct 10, 2000
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app pub date -
Jan 19, 1998
filing date -
Jan 19, 1998
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Abstract
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable Length Interconnect Architecture (VLI). Synthesis mapping exploits the diversified and symmetric resources of the VGA and VLI to efficiently pack function development into logic units of matched granularity and to transfer signals between logic units with interconnect lines of minimal length.
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