Circuit of reducing transmission delay for synchronous DRAM
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United States of America Patent
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Oct 10, 2000
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N/A
app pub date -
Dec 10, 1997
filing date -
Dec 10, 1997
priority date (Note) -
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Abstract
A circuit for reducing the transmission delay of the SDRAM by using a cascade-amplifying scheme. The circuit principally encompasses a memory array core for storing data, a main amplifier for initially amplifying the data, an MO-pair receiving amplifier for recognizing and amplifying the data, and an output neighborhood for outputting the data when the data convey a log data path. When the required data output from the memory array core is amplified by the main amplifier, the differential level of the required data will appear at both the far end and the near end of the data path. Therefore, the transmitted data at the far end can be amplified again as long as the differential level is sufficient.
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