Latching wordline driver for multi-bank memory
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United States of America Patent
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-
Oct 10, 2000
Grant Date -
N/A
app pub date -
Jan 11, 1999
filing date -
Mar 11, 1997
priority date (Note) -
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Abstract
A memory device is described which includes latching wordline driver circuits. The wordline driver circuits include a latch responsive to phase lines of an address tree decode configuration. The latch has been described as a single latching transistor which allows transitions in shared row address lines while maintaining an active wordline signal. The latching wordline driver is particularly useful in multi-bank memory devices where row address lines are shared between the memory banks.
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