Floating point addition pipeline configured to perform floating point-to-integer and integer-to-floating point conversion operations

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United States of America Patent

PATENT NO 6131104
SERIAL NO

09049851

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Abstract

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An optimized multimedia execution unit configured to perform vectored floating point and integer instructions. In one embodiment, the execution unit includes an add/subtract pipeline having far and close data paths. The far data path handles effective addition operations, as well as effective subtraction operations for operands having an absolute exponent difference greater than one. The close data path, conversely, handles effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close data path includes an adder unit configured to generate a first and second output value. The first output value is equal to the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. The two output values are conveyed to a multiplexer unit, which selects one of the output values as a preliminary subtraction result based on a final selection signal generated from a plurality of preliminary selection signals that are based on the carry in signal to the most significant bit of the first adder output value. Selection of the first or second output value in the close data path effectuates the round-to-nearest operation for the output of the adder. The execution unit may also be configured, in another embodiment, to perform floating point-to-integer and integer-to-floating point conversions. The floating point-to-integer conversions may be executed in the far data path, with the integer-to-floating point instructions executed in the close data path.

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Patent Owner(s)

Patent OwnerAddress
ADVANCED SILICON TECHNOLOGIES LLC10 THORNTON LANE LEE NH 03861

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Oberman, Stuart F Sunnyvale, CA 68 2361

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