Importance

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Abstract

A method, apparatus and system for controlling the reading and writing of flash memories including a write control section, a plurality of read enable control signal lines and a read control section. The write control section configured to supply a write command, a write head address and first data to each of the flash memories through a bus at a predetermined timing to cause one of the flash memories to perform a write mode for writing sequentially first data from a memory address of a corresponding one of the flash memories which is accessed by the write head address in response to the write command, the write head address and first data being supplied at a predetermined timing without fetching any external signal within a first time period. The plurality of read enable control signal lines connected to the plurality of flash memories, respectively, to assign individually a plurality of read enable control signals to the flash memories via the signal lines. The read control section configured to supply a read command and a read head address to another one of the flash memories at a predetermined timing within a second time period which is at least shorter than the first time period through the bus to cause the another one of the flash memories to perform a read mode for reading sequentially second data from a memory address of the another one of the flash memories which is accessed by the read head address in response to the read command within the second time period, set the second data to an output port, and send the second data at the output port to the bus in response to an assigned one of the read enable control signals.

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First Claim