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Abstract

A novel apparatus and method is disclosed to assure validity of data accessed from synchronous memory during a 'read' operation, wherein the synchronous memory is operating synchronously at a high frequency system clock. The invention comprises a programmable delay module which generates a skewed clock signal which is used to clock in data read from the synchronous memory. The programmable delay module generates the skewed clock signal by adding programmable time delays to the system clock signal. The inserted delay increases the data valid window time available for the 'read' operation and allows sufficient setup and hold time for valid data to be read by a memory controller.

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First Claim