Compliant interface for semiconductor chip and method therefor
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United States of America Patent
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Oct 17, 2000
Issued Date -
N/A
app pub date -
Apr 24, 1997
filing date -
Sep 20, 1994
priority date (Note) -
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Abstract
A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The complaint interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.
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