Semiconductor substrate and method of manufacturing semiconductor device
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United States of America Patent
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Oct 17, 2000
Grant Date -
N/A
app pub date -
Jan 20, 1998
filing date -
Jan 23, 1997
priority date (Note) -
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Abstract
A contact alignment mark (18A) is provided in an interlayer insulating film (17), and a wiring alignment mark (19A) is formed above a gate alignment mark (15A) so that the size of the wiring alignment mark (19A) is slightly larger than the gate alignment mark (15A). At the same time, all the other alignment marks at the lower side are shielded by a shield film (19S). All the alignment marks at the lower side are shielded by the opaque alignment mark and the opaque shield film, whereby the alignment marks can be successively formed while stacked on one another.
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