Nonvolatile semiconductor memory device capable of preventing data from being written in error
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United States of America Patent
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Oct 17, 2000
Grant Date -
N/A
app pub date -
Feb 3, 1998
filing date -
Feb 3, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory cell array includes a plurality of memory cells connected in series, and each of the memory cells is constituted of an EEPROM. A bit line is connected to one end of the memory cell array, and a source line is connected to the other end thereof. A source line bias circuit is connected to the source line. The source line bias circuit supplies a voltage, which is higher than a power supply voltage and lower than an erase voltage in a data write mode, to the source line to precharge the voltage of channels of the memory cells higher than the power supply voltage. After that, a voltage is applied to the control gates of the memory cells to boost the precharged voltage further by capacitance coupling of the channels and control gates. It is thus possible to prevent data from being erroneously written to a memory cell for writing '1' data.
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