Configurable memory block
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Oct 17, 2000
Grant Date -
N/A
app pub date -
Feb 24, 1999
filing date -
Feb 24, 1999
priority date (Note) -
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Abstract
A circuit and method comprising a memory array and a plurality of address circuits. The memory may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The plurality of address circuits may each be configured to generate one of said internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal.
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