US Patent No: 6,134,516
Number of patents in Portfolio can not be more than 2000
Simulation server system and method
Stats
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Oct 17, 2000
Issued date -
Feb 5, 1998
filing date -
09/019,384
serial no -
In Force
status
Importance
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Abstract
The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. A Simulation server in accordance with an embodiment of the present invention allows multiple users to access the same reconfigurable hardware unit to effectively simulate and accelerate the same or different user designs in a time-shared manner in both a network and a non-network environment. The server provides the multiple users or processes to access the reconfigurable hardware unit for acceleration and hardware state swapping purposes. The Simulation server includes the scheduler, one or more device drivers, and the reconfigurable hardware unit. The scheduler in the Simulation server is based on a preemptive round robin algorithm. The server scheduler includes a simulation job queue table, a priority sorter, and a job swapper.
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First Claim
Related Publications
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 5,475,830 Structure and method for providing a reconfigurable emulation circuit without hold time violations | 88 | 1992 | |
| 5,352,123 Switching midplane and interconnection system for interconnecting large numbers of signals | 83 | 1992 | |
| 5,452,239 Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system | 236 | 1993 | |
| 5,448,522 Multi-port memory emulation using tag registers | 28 | 1994 | |
| 5,452,231 Hierarchically connected reconfigurable logic assembly | 110 | 1994 | |
| 5,448,496 Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system | 92 | 1994 | |
| 5,477,475 Method for emulating a circuit design using an electrically reconfigurable hardware emulation apparatus | 59 | 1994 | |
| 5,612,891 Hardware logic emulation system with memory capability | 59 | 1995 | |
| 5,657,241 Routing methods for use in a logic emulation system | 36 | 1995 | |
| 5,661,662 Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation | 66 | 1995 | |
| 5,644,515 Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation | 38 | 1995 | |
| 5,649,167 Methods for controlling timing in a logic emulation system | 25 | 1995 | |
| 5,563,829 Multi-port memory emulation using tag registers | 22 | 1995 | |
| 5,841,967 Method and apparatus for design verification using emulation and simulation | 66 | 1996 | |
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| 4,306,286 Logic simulation machine | 172 | 1979 | |
| 4,386,403 System and method for LSI circuit analysis | 47 | 1979 | |
| 4,503,386 Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks | 63 | 1982 | |
| 4,656,580 Logic simulation machine | 111 | 1982 | |
| 4,593,363 Simultaneous placement and wiring for VLSI chips | 152 | 1983 | |
| 4,862,347 System for simulating memory arrays in a logic simulation machine | 102 | 1986 | |
| 4,695,999 Cross-point switch of multiple autonomous planes | 64 | 1986 | |
| 4,849,904 Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices | 53 | 1987 | |
| 5,003,487 Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis | 91 | 1988 | |
| 5,146,460 Logic simulation using a hardware accelerator together with an automated error event isolation and trace facility | 69 | 1990 | |
| 5,263,149 Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles | 36 | 1991 | |
| 5,721,953 Interface for logic simulation using parallel bus for concurrent transfers and having FIFO buffers for sending data to receiving units when ready | 12 | 1996 | |
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| 4,787,061 Dual delay mode pipelined logic simulator | 55 | 1986 | |
| 4,736,338 Programmable look up system | 31 | 1986 | |
| 4,744,084 Hardware modeling system and method for simulating portions of electrical circuits | 129 | 1987 | |
| 5,377,124 Field programmable printed circuit board | 45 | 1989 | |
| 5,126,966 High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs | 49 | 1990 | |
| 5,371,390 Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits | 75 | 1992 | |
| 5,504,354 Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits | 33 | 1994 | |
| 5,661,409 Field programmable printed circuit board | 24 | 1995 | |
| 5,654,564 Interconnect structure with programmable IC for interconnecting electronic components, including circuitry for controlling programmable IC | 48 | 1996 | |
| 5,850,537 Pipe lined static router and scheduler for configurable logic system performing simultaneous communications and computation | 39 | 1997 | |
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| 4,697,241 Hardware logic simulator | 105 | 1985 | |
| 4,914,612 Massively distributed simulation engine | 78 | 1988 | |
| 5,109,353 Apparatus for emulation of electronic hardware system | 177 | 1988 | |
| 5,036,473 Method of using electronically reconfigurable logic circuits | 244 | 1989 | |
| 5,114,353 Multiple connector arrangement for printed circuit board interconnection | 21 | 1991 | |
| 5,259,006 Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like | 104 | 1991 | |
| 5,329,470 Reconfigurable hardware emulation system | 133 | 1993 | |
| 5,796,623 Apparatus and method for performing computations with electrically reconfigurable logic devices | 33 | 1996 | |
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| 4,541,071 Dynamic gate array whereby an assembly of gates is simulated by logic operations on variables selected according to the gates | 41 | 1983 | |
| 4,752,887 Routing method for use in wiring design | 71 | 1986 | |
| 4,747,102 Method of controlling a logical simulation at a high speed | 32 | 1986 | |
| 4,945,503 Hardware simulator capable of reducing an amount of information | 42 | 1987 | |
| 4,924,429 Hardware logic simulator | 50 | 1988 | |
| 5,041,986 Logic synthesis system comprising a memory for a reduced number of translation rules | 32 | 1989 | |
| 5,467,462 Event driven logic simulator for partial simulation | 32 | 1992 | |
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| 4,642,487 Special interconnect for configurable logic array | 396 | 1984 | |
| 4,706,216 Configurable logic element | 472 | 1985 | |
| 4,758,985 Microprocessor oriented configurable logic element | 252 | 1986 | |
| 4,870,302 Configurable electrical circuit having configurable logic elements and configurable interconnects | 680 | 1988 | |
| 5,343,406 Distributed memory architecture for a configurable logic array and method for using distributed memory | 236 | 1989 | |
| 5,224,056 Logic placement using positionally asymmetrical partitioning algorithm | 124 | 1991 | |
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| 5,233,539 Programmable gate array with improved interconnect structure, input/output structure and configurable logic block | 151 | 1989 | |
| 5,260,881 Programmable gate array with improved configurable logic block | 73 | 1989 | |
| 5,128,871 Apparatus and method for allocation of resoures in programmable logic devices | 189 | 1990 | |
| 5,231,588 Programmable gate array with logic cells having symmetrical input/output structures | 100 | 1990 | |
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| 4,578,761 Separating an equivalent circuit into components to detect terminating networks | 30 | 1983 | |
| 4,577,276 Placement of components on circuit substrates | 118 | 1983 | |
| 4,908,772 Integrated circuits with component placement by rectilinear partitioning | 135 | 1987 | |
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| 4,942,536 Method of automatic circuit translation | 56 | 1986 | |
| 4,803,636 Circuit translator | 54 | 1986 | |
| 5,046,017 Wiring design for semiconductor integrated circuit | 58 | 1988 | |
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| 4,823,276 Computer-aided automatic wiring method for semiconductor integrated circuit device | 48 | 1987 | |
| 5,784,591 Parallel simulator for semiconductor integrated circuit | 6 | 1995 | |
| 5,603,015 Logic simulation apparatus for executing simulation of a circuit | 18 | 1995 | |
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| 4,700,187 Programmable, asynchronous logic cell and array | 138 | 1985 | |
| 4,918,440 Programmable logic cell and array | 152 | 1986 | |
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| 4,942,615 Gate processor arrangement for simulation processor system | 38 | 1988 | |
| 5,258,932 PLA simulation method | 24 | 1991 | |
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| 4,918,594 Method and system for logical simulation of information processing system including logic circuit model and logic function model | 53 | 1987 | |
| 5,231,589 Input/output pin assignment method | 34 | 1990 | |
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| 4,835,705 Interconnection area decision processor | 53 | 1987 | |
| 4,876,466 Programmable logic array having a changeable logic structure | 107 | 1988 | |
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| 5,084,824 Simulation model generation from a physical data base of a combinatorial circuit | 136 | 1990 | |
| 5,189,628 System and method for partitioning PLA product terms into distinct logical groups | 24 | 1991 | |
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| 4,777,606 Method for deriving an interconnection route between elements in an interconnection medium | 141 | 1986 | |
| 5,193,068 Method of inducing off-circuit behavior in a physical model | 16 | 1990 | |
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| 4,922,432 Knowledge based method and apparatus for designing integrated circuits using functional specifications | 169 | 1988 | |
| 5,197,016 Integrated silicon-software compiler | 100 | 1989 | |
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| 5,081,602 Computer simulator for electrical connectors | 34 | 1989 | |
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| 5,093,920 Programmable processing elements interconnected by a communication network including field operation unit for performing field operations | 46 | 1989 | |
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| 5,375,074 Unboundedly parallel simulations | 30 | 1990 | |
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| 5,513,339 Concurrent fault simulation of circuits with both logic elements and functional circuits | 116 | 1994 | |
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| 4,949,275 Semiconductor integrated circuit device made by a standard-cell system and method for manufacture of same | 52 | 1985 | |
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| 4,931,946 Programmable tiles | 50 | 1988 | |
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| 4,872,125 Multiple processor accelerator for logic simulation | 60 | 1988 | |
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| 4,621,339 SIMD machine using cube connected cycles network architecture for vector processing | 157 | 1983 | |
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| 4,935,734 Semi-conductor integrated circuits/systems | 145 | 1986 | |
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| 2002/0186,837 Multiple prime number generation using a parallel prime number search algorithm | 2001 | ||
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| 4,882,690 Incremental logic synthesis method | 81 | 1986 | |
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| 5,023,775 Software programmable logic array utilizing "and" and "or" gates | 104 | 1990 | |
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| 5,253,181 Programmable one-board computer, and methods of verification of logic circuit and alteration to actual circuit using the programmable one-board computer | 41 | 1990 | |
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| 4,901,259 Asic emulator | 82 | 1988 | |
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| 4,791,602 Soft programmable logic array | 60 | 1986 | |
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| 5,053,980 Method and apparatus for logic simulation | 35 | 1989 | |
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| 5,140,526 Partitioning of Boolean logic equations into physical logic devices | 79 | 1989 | |
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| 4,901,260 Bounded lag distributed discrete event simulation method and apparatus | 65 | 1987 | |
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| 5,452,227 Method and apparatus for converting a programmable logic device designed into a selectable target gate array design | 51 | 1991 | |
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| 5,272,651 Circuit simulation system with wake-up latency | 25 | 1990 | |
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| 5,425,036 Method and apparatus for debugging reconfigurable emulation systems | 229 | 1992 | |
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| 4,811,214 Multinode reconfigurable pipeline computer | 210 | 1986 | |
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| 4,768,196 Programmable logic array | 54 | 1986 | |
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| 4,612,618 Hierarchical, computerized design of integrated circuits | 106 | 1983 | |
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| 4,815,003 Structured design method for high density standard cell and macrocell layout of VLSI chips | 142 | 1987 | |
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| 4,488,354 Method for simulating and testing an integrated circuit chip | 61 | 1981 | |
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| 4,951,220 Method and apparatus for manufacturing a test-compatible, largely defect-tolerant configuration of redundantly implemented, systolic VLSI systems | 37 | 1988 | |
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| 5,748,875 Digital logic simulation/emulation system | 82 | 1996 | |
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| 4,740,919 Electrically programmable logic array | 35 | 1986 | |
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| 4,656,592 Very large scale integrated circuit subdivided into isochronous regions, method for the machine-aided design of such a circuit, and method for the machine-aided testing of such a circuit | 101 | 1984 | |
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| 4,819,150 Array for simulating computer functions for large computer systems | 19 | 1985 | |
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| 4,675,832 Visual display logic simulation system | 75 | 1984 | |
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| 4,965,739 Machine process for routing interconnections from one module to another module and for positioning said two modules after said modules are interconnected | 75 | 1989 | |
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| 4,786,904 Electronically programmable gate array having programmable interconnect lines | 166 | 1986 | |
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| 4,682,440 Animal trap | 28 | 1986 | |
| 4,849,928 Logic array programmer | 41 | 1987 | |
| 4,827,427 Instantaneous incremental compiler for producing logic circuit designs | 101 | 1987 | |
| 5,051,938 Simulation of selected logic circuit designs | 118 | 1989 | |
| 5,546,562 Method and apparatus to emulate VLSI circuits within a logic simulator | 124 | 1995 | |