Tri-state bus contention circuit preventing false switching caused by poor synchronization
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United States of America Patent
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-
Oct 17, 2000
Grant Date -
N/A
app pub date -
Mar 31, 1998
filing date -
Mar 31, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method of avoiding contention on a communications bus using an improved tri-state driver, which negates one of the internal driver signals during a restore region of the driver cycle, such that the driver cannot switch to the high state when there is poor synchronization that delays one of the internal driver signals. Restoring logic provides a first logic signal and a second logic signal. An input gate is asserted to an active level in response to the first logic signal, and gating logic conditionally enables the input gate in response to the second signal.
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