Memory controller supporting DRAM circuits with different operating speeds
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United States of America Patent
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Oct 17, 2000
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N/A
app pub date -
Aug 13, 1997
filing date -
Aug 13, 1997
priority date (Note) -
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Abstract
A computer system including synchronous dynamic random access memory (SDRAM) circuits that are capable of operating at different frequencies. A memory controller generates multiple clock signals with appropriate frequencies for use by the SDRAM memory devices. Asynchronous data queues are used to provide data transfers between the SDRAM memory and the processor or other bus master devices residing on a peripheral bus. Upon initialization, the computer system determines the type of SDRAM devices present and provides status information to the memory controller which, in response, generates appropriate clock signals to the SDRAM memory circuits.
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