System and method for dicing semiconductor components
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United States of America Patent
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Oct 24, 2000
Grant Date -
N/A
app pub date -
Jul 6, 1998
filing date -
Jul 6, 1998
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A method and system for dicing semiconductor components, such as bare dice and chip scale packages, are provided. Initially, the semiconductor components are contained on a wafer or a panel. Next, an insert that includes a base and an adhesive layer, is used to support the substrate for separation into separate components by sawing or other process. The insert with the separated components retained thereon, is then transferred to a carrier tray constructed according to JEDEC standards. The carrier tray is adapted for stacking and for handling by conveyors, magazines and other standard equipment. The system includes the substrate, the insert, and the standardized carrier tray.
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