Low cost DRAM metallization

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6137180
SERIAL NO

09038211

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Disclosed is a low cost contact and interconnect layer and method for fabricating the same. A contact via is opened within an insulating layer, exposing a circuit node (e.g., transistor active area within a semiconductor substrate). The via is filled with a chemical vapor deposited (CVD) titanium silicide layer, forming electrical contact with the circuit node. The silicide layer may simultaneously form the interconnect layer for one embodiment. In other embodiments, the interconnect layer may comprise a metal strap over the titanium silicide layer, or a metal layer over an etched-back titanium silicide plug in the contact via. For any of these embodiments, the contact via may be opened after the formation of interconnect trenches, the via extending from the bottom of a trench to the circuit node. CVD provides good step coverage of the via within the trench, despite the higher aspect ratio. The interconnect layer is deposited and etched back, such that the interconnect lines are defined by the trenches.

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Patent Owner(s)

Patent OwnerAddress
ROUND ROCK RESEARCH LLC26 DEER CREEK LANE MT KISCO NY 10549

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sandhu, Gurtej S Boise, ID 1223 33846
Sharan, Sujit Boise, ID 229 3419

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