Method for operating a non-volatile memory cell arrangement
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United States of America Patent
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Oct 24, 2000
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N/A
app pub date -
Jan 28, 1999
filing date -
Aug 1, 1996
priority date (Note) -
Expired
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Abstract
In order to increase the storage density, in a memory cell arrangement having MOS transistors as memory cells which has as gate dielectric, a dielectric triple layer having a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, the silicon oxide layers each having a thickness of at least 3 nm, the information is stored using multi-value logic with up to 2.sup.6 values. In this case, use is made of the fact that these memory cells have a time period greater than 1000 years for data retention and their threshold voltage has a very small drift.
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