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Abstract

A floating point arithmetic unit provides consistent propagation of NaNs le performing high precision calculations on hardware designed to perform lower precision calculations. In one embodiment, the floating point arithmetic unit is provided with a microcode memory that stores more than one set of NaN propagation rules. In operation, the floating point arithmetic unit accesses one of the sets of NaN propagation rules according to the precision of the calculation being performed. A method of performing calculations in a floating point arithmetic unit includes dynamically determining if a calculation to be performed is to be a quad precision calculation or a double precision calculation. If it is determined that a quad precision calculation is to be performed, quad precision NaN propagation rules are selected and a quad precision calculation is performed using the selected quad precision NaN propagation rules. Likewise, if it is determined that a double precision calculation is to be performed, double precision NaN propagation rules are selected and a double precision calculation is performed using the selected double precision NaN propagation rules. By providing more than one set of NaN propagation rules and selecting one of the sets of NaN propagation rules depending on the precision of the calculation being performed, propagation of NaNs in conformance with IEEE standards can be assured. The method and apparatus are easily extended to higher precision calculations to ensure proper propagation of NaNs regardless of the precision calculation.

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