Address translation system having first and second translation look aside buffers
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United States of America Patent
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Oct 24, 2000
Grant Date -
N/A
app pub date -
Dec 24, 1997
filing date -
Dec 24, 1997
priority date (Note) -
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Abstract
A memory system for providing rapid access to cached data includes a cache, a first TLB that stores address translation entries in a truncated form for fast access to data in the cache, and a second TLB that stores full address translation entries for accurate translation. The first TLB generates the tentative physical address quickly and initiates access to the cache using the tentative physical address. A way identified using the tentative physical address is read out of the cache and compared with a validated physical address provided by the second TLB. The initiated access is allowed to complete when the tentative and validated physical addresses match.
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