Importance

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Abstract

A protocol and internal link system of a micro-controller in which components, interconnected by a parallel BUS link, exchange during a transaction successive messages on a plurality of clock cycles. A master transmitting component transmits, on a current clock cycle, to an addressee slave receiver component, an instruction message, encoded on N+p bits, and comprising a main field, N bits, and an auxiliary field, p bits, comprising an operation code, a signature identifying master and slave component and their transaction. A proof of transmission message and an acknowledgement message are transmitted from the master component to the slave component and vice versa on the following clock cycle. These steps are repeated on at least one subsequent clock cycle.

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First Claim