Method for detecting process sensitivity to integrated circuit layout by compound processing
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United States of America Patent
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Oct 31, 2000
Grant Date -
N/A
app pub date -
Sep 16, 1998
filing date -
Sep 16, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus that uses compound processing for detecting defects in integrated circuits involves processing two portions of a semiconductor wafer differently according to a first and a second process. The first process and the second process are performed on alternating columns on the wafer. Image subtraction is used to detect differences between the layouts in adjacent columns. After differences are detected, the layout is examined to determine whether the difference represents a defect. If so, the design rules of the layout can be changed to accommodate a wider process variation.
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