Clock synchronous memory
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Oct 31, 2000
Grant Date -
N/A
app pub date -
Jul 15, 1999
filing date -
Jul 15, 1998
priority date (Note) -
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Abstract
A clock synchronous memory capable of accurately synchronizing a clock with data is provided. The clock synchronous memory has a fine delay control circuit for precisely synchronizing a clock with data. The fine delay control circuit uses a first type delay unit and a second type delay unit and allows the clock to pass through at least one of the first and second type delay units, thereby finely adjusting a delay time of the clock.
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