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Abstract

An interface device between first and second computer busses includes a data input having a first data width, a data output having a second data width different from the first data width, an address input and an address output. The interface device includes constructed on a single integrated circuit parallel FIFOs, a multiplexer circuitry having a first input connected to the output of a first FIFO, a second input connected to the output of a second FIFO, an output and a control input, and an address translation circuit translating first addresses received at the address input into second addresses supplied to the address output. The less significant bit of the address input coupled to the control input of the multiplexer circuitry. The integrated circuit may further include a digital signal processor coupled to said address input and said data input. The two FIFOs are bidirectional and include byte enable outputs. The integrated circuit further includes a north bridge circuitry including a DRAM memory controller and a PCI bus interface, a cardbus controller circuitry, scatter-gather DMA (direct memory access) circuitry coupled to said address output and a bus control block including both master and slave circuits coupled to said data output.

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First Claim