Importance

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Abstract

A communications bus for providing communication between a master processor and a plurality of slave processors, each including a central processing unit, the slave processors located remote from the master processor, the bus selectively resets a slave processor and includes first, second, third and fourth communication paths. The first communication path transmits signals including destination addresses from the master processor to each of the plurality of slave processors. The second communication path transmits a strobe signal from the master processor to each of the plurality of slave processors. The strobe signal has first and second states. The third communication path transmits a reset signal from the master processor to each of the plurality of slave processors. The reset signal has first and second states. The fourth communication path transmits a disable signal from the master processor to each of the plurality of slave processors. The disable signal has first and second states. The addressed slave processor when the strobe signal is in the first state is reset when the reset signal is in the first state and the disable signal is in the first state. The central processing unit of the address slave processor is reset when the strobe signal is in the first state and the reset signal is in the first state and the disable signal is in the second state. The central processing unit of the addressed slave processor exits reset when the reset signal is in the second state and the disable signal is in either the first or second state.

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First Claim