Data flow integrated circuit architecture
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United States of America Patent
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Nov 7, 2000
Grant Date -
N/A
app pub date -
Oct 16, 1998
filing date -
Oct 16, 1998
priority date (Note) -
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Abstract
Pre-designed and verified data-driven hardware cores (intellectual property, functional blocks) are assembled to generate large systems on a single chip. Token transfer between cores is achieved upon synchronous assertion, over dedicated connections, of a one-bit ready signal by the transmitter and a one-bit request signal by the receiver. The ready-request signal handshake is necessary and sufficient for token transfer. There are no combinational paths through the cores, and no latches or master controller are used. The architecture and interface allow a significant simplification in the design and verification of large systems integrated on a single chip.
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