Debugging system

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United States of America Patent

PATENT NO 6145099
SERIAL NO

08910800

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Abstract

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In a debugging system for use in realizing simultaneously complete observation of internal operation and reproduction of malfunction actually caused in a target system which includes an integrated circuit, such as a microprocessor, contents of a memory and an internal initial state of the target system are snooped and stored in a snoop unit and a trace memory, respectively, both of which are included in a probe unit attached to the target system. The internal operation and the reproduction are simulated by a software simulator model by the use of the contents and the internal initial state which are stored in the trace memory and which are sent from the probe unit.

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Patent Owner(s)

  • NEC CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Shindou, Keisuke Tokyo, JP 1 35

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