Method for forming self-aligned selective silicide layer using chemical mechanical polishing in merged DRAM logic
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United States of America Patent
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Nov 14, 2000
Grant Date -
N/A
app pub date -
Apr 26, 1999
filing date -
Jun 8, 1998
priority date (Note) -
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Abstract
A semiconductor device including a first area where a silicide layer is formed only on a gate electrode, and a second area where a silicide layer is formed both on the gate electrode and on source and drain areas is produced by a method wherein a polishing stopper and an oxide layer are sequentially stacked, the gate electrode is exposed in a self-aligned manner, and then a first silicide layer is formed to thereby suppress misalignment in the process of manufacturing a semiconductor device having a fine linear width. In the first area, when first and second insulating layers are stacked and contact holes are formed directly connected to the semiconductor substrate, a second silicide layer is formed at the bottoms of the contact holes, to reduce contact resistance and leakage current.
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