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Abstract

A background suppression technique uses well-controlled and repeatable charge skimming operations to increase the charge capacities of the integration capacitors of integrated focal plane readout unit cells. A MOSFET (Q1) is connected to an integration capacitor (C.sub.int) from which the quantity of stored charge is to be reduced. During each photocurrent integration period, the MOSFET is driven with a 'skimming pulse' (V.sub.sk) to draw charge from the capacitor. The skimming pulse is substantially shorter than an integration period, reducing the amount of noise contributed by the MOSFET's noise mechanisms, and has an amplitude great enough to drive the MOSFET into its strong inversion mode, making the quantity of the removed charge relatively insensitive to variations in MOSFET threshold voltage. The charge skimming pulse is arranged to reduce the charge on the capacitor almost, but not quite, to zero, so that the entire integration period remains utilized.

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First Claim