Polycide gate structure with intermediate barrier
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United States of America Patent
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Nov 14, 2000
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N/A
app pub date -
Nov 24, 1997
filing date -
Nov 24, 1997
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Abstract
A CMOS gate structure comprises a multilayered polysilicon structure and a deposited silicide layer, with a nitridized silicide barrier layer formed therebetween. The multilayered polysilicon will exhibit a relatively large grain size and uniform structure. The deposited silicide layer is annealed to mimic the polysilicon grain size and structure. The combination of the tailored grain structure with the intermediate barrier layer results in a gate structure that is essentially impervious to subsequent dopant diffusions.
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