Dual barrier and conductor deposition in a dual damascene process for semiconductors
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United States of America Patent
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Nov 14, 2000
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N/A
app pub date -
May 24, 1999
filing date -
May 24, 1999
priority date (Note) -
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Abstract
An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.
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