Importance

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Abstract

A ferroelectric integrated circuit memory includes a memory cell having a first ferroelectric capacitor, one electrode of which is connected to a first bit line through a first transistor and the other electrode of which is connected to a plate line; and a second ferroelectric capacitor, one electrode of which is connected to a second bit line through a second transistor and the other electrode of which is connected to the plate line. The plate line is parallel to the bit lines. The plate line is at 1/2 Vdd. The cell is written to by driving both bit lines either to Vdd or zero volts. The cell is read by driving one bit line to Vdd and the other to zero volts, and sensing the voltage change on the plate line. A shunt system holds the isolated node to the same voltage as the plate line when the row is not selected, thus providing a ferroelectric memory architecture that is unaffected by changes, such as aging, in the ferroelectric material, and has no disturb voltages.

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First Claim