Method for fabrication of programmable interconnect structure

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United States of America Patent

PATENT NO 6150199
SERIAL NO

09405979

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Abstract

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In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

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Patent Owner(s)

  • QUICKLOGIC CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bechtel, Richard L Sunnyvale, CA 14 519
Birkner, John M Portola Valley, CA 21 976
Chan, Andrew K Palo Alto, CA 47 1833
Chua, Hua-Thye Los Altos Hills, CA 20 897
Thomas, Mammen San Jose, CA 78 985
Whitten, Ralph G San Jose, CA 34 1683

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