Integrated circuit architecture having an array of test cells providing full controllability for automatic circuit verification
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Nov 21, 2000
Grant Date -
N/A
app pub date -
Feb 12, 1999
filing date -
Jun 18, 1991
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A new circuit architecture is provided for testing digital integrated circuits which allows one to arbitrarily force any combination of logic values to be simultaneously driven onto any combination of internal nets. This allows all of the connections to each internal logic cell, and the logic cell itself, to be verified by applying a set of test patterns to each logic cell individually. In this way, the integrity of the entire device can be verified without having knowledge of the operation of the circuit as a whole.
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