Circuit and method for minimizing recovery time
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United States of America Patent
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Nov 21, 2000
Grant Date -
N/A
app pub date -
Aug 3, 1998
filing date -
Aug 3, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.
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