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Abstract

Integrated circuit memory devices include first and second spaced-apart memory banks in an integrated circuit substrate. A pad block in the integrated circuit substrate is located between the first and second spaced-apart memory banks. An input/output block in the integrated circuit substrate is connected to the pad block to receive input data from external of the integrated circuit memory device via the pad block and to transmit output data to external of the integrated circuit memory device via the pad block. A delay locked loop in the integrated circuit substrate is responsive to an external clock signal to generate an internal clock signal. An interface logic block in the integrated circuit substrate is responsive to the internal clock signal to control the first and second memory banks and the input/output block in response to the internal clock signal. A single data shift block in the integrated circuit substrate is located between the pad block and one of the first and second spaced-apart memory banks. The single data shift block is connected to the input/output block by a first plurality of lines and to both of the first and second memory banks by a second plurality of lines that is an integer multiple of the first plurality. The single data shift block converts serial data on the first plurality of lines to parallel data on the second plurality of lines and converts parallel data on the second plurality of lines to serial data on the first plurality of lines. The invention may be used in any integrated circuit memory device. However, the invention is preferably used in a packet type integrated circuit memory device that operates on packets of data address and control signals, such as a Rambus integrated circuit memory device.

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First Claim