Importance

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Abstract

A carry logic circuit is provided for an array of configurable logic blocks (CLBs), wherein each configurable logic block includes an array of logic cells arranged in rows and columns. At least one column of logic cells includes a carry output signal selection circuit. At least one other column of logic cells includes a carry initialization circuit. The locations of the carry output signal selection circuits and carry initialization circuits are identical in each of the CLBs, and the CLBs have identical first columns of configurable logic cells and identical second columns of configurable logic cells. Dedicated routing circuitry is provided for column shifting the carry chains between vertically adjacent CLBs. Column shifting is performed such that a column of logic cells in one CLB is coupled to a non-corresponding column of logic cells in a vertically adjacent CLB. For example, the routing circuitry may perform column shifting such that a first column of logic cells in a first CLB is connected to a second column of logic cells in a vertically adjacent second CLB. Also described are methods for performing a carry logic function in an FPGA.

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First Claim