Importance

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Abstract

A sense amplifier having four NMOS transistors and two resistors is operable at voltage supplies less than 2.5 volts and has a fast response time. The drain terminals of two of the NMOS transistors, each receiving an input voltage signal at its gate terminal, provide a differential output voltage signal across the two resistors. The source terminals of these two NMOS transistors are coupled to the drain and gate terminals of a cross-coupled second pair of NMOS transistors. The amplifier exhibits negative input capacitance at each of its input terminals. The amplifier has a common mode input voltage that is substantially equal to the common mode output voltage, facilitating the cascading of many stages of the amplifier. Each stage of a multi-stage cascade of the amplifiers has a greater than unity voltage gain if driving a low capacitance line or a smaller than unity gain if driving a high capacitance line.

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First Claim