Importance

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Abstract

A circuit for reducing the ground and power supply bounce of the output drivers in a group of I/O cells. A replica I/O cell is part of a delay locked loop which uses closed-loop feedback control to determine the magnitude of a bias current needed to cause the delay through the replica cell to be equal to a reference value. By forcing the delay through the replica cell to be equal to a desired reference value, the magnitude of bias current required to control the delay through each of the I/O cells in an I/O ring so that the delay approaches the reference value can be determined. As a result, by properly selecting the reference delay value, the magnitude of the bias current required to compensate for delay variations arising from multiple sources (e.g., PVT) can be determined. Since this reduces the rate of change of the current in the output drivers of the actual I/O cells, the induced voltage responsible for the ground and/or power supply bounce in those cells is reduced.

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First Claim