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Abstract

A ternary content addressable memory (CAM) cell. For one embodiment, the ternary CAM cell includes a first memory cell, a compare circuit, a second memory cell and a mask circuit. The first memory cell is coupled to a first pair of bit lines that carries data to and from the first memory cell. The compare circuit receives comparand data on a pair of compare signal lines, and compares the comparand data with the data stored in the first memory cell. The compare circuit includes a pair of transistors and a match transistor. The pair of transistors receives the comparand data on the compare signal lines and also receives the data stored in the first memory cell. The match transistor determines the state of a match line. The second memory cell stores mask data that may mask the comparison result such that it does not affect the logical state of the match line.

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First Claim