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Abstract

Integrated circuit memory devices having synchronous wave pipelining capability include a memory cell array and circuitry therein that is electrically coupled to the memory cell array and latches read data accessed from the memory cell array during a prior ith cycle of an internal clock signal (PCLK), in-sync with an i+1th cycle of the internal clock signal. This delayed latching of previously accessed read data increases the data latch margin and improves device reliability even if worst case processing conditions are encountered. This latching circuit includes a register that is responsive to a plurality of register input control signals (DLLi) and a pipelined register input control circuit that generates the plurality of register input control signals in response to a column select disable signal (CSLD). The latching circuit also preferably includes a column select control circuit that latches a value of a bank select signal (CAi.sub.-- BANK) when the internal clock signal is in a first logic state and passes the latched value of the bank select signal as the column select disable signal upon transition of the internal clock signal from the first logic state to a second logic state.

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First Claim