Loadable up-down counter with asynchronous reset
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United States of America Patent
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Dec 5, 2000
Grant Date -
N/A
app pub date -
Dec 18, 1998
filing date -
Dec 18, 1998
priority date (Note) -
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Abstract
In an FPGA having four-input lookup tables (LUTs) with parallel two-input AND gates receiving two of the four LUT input signals, associated registers, and a carry chain receiving one input signal from the AND gate output, a loadable up-down counter is formed by connecting the register output to one of the terminals serving as both a LUT input terminal and an AND gate input terminal. A load control signal is connected to another input terminal common to the LUT and the AND gate. Thus the AND gate disables the carry chain during loading of the counter and applies the count value to the carry chain during counting.
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