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Abstract

A programmable logic device, such as a field programmable gate array or arithmetic array, comprises: a rectilinear array of logic cells 10 pitched with first and second general cell pitches P.sub.1, P.sub.2, respectively, in first and second axial directions, respectively, of the array; a first array of wires 12 each extending generally in the first direction between a respective pair of the cells which have a pitch of N.sub.1 .times.P.sub.1, where N.sub.1 is an integer greater than one, the first wire array having a pitch in the second direction generally equal to N.sub.2 .times.P.sub.2, where N.sub.2 is an integer greater than zero; and a second array of wires 14 each extending generally in the second direction between a respective pair of the cells which have a pitch of N.sub.1 .times.P.sub.2, the second wire array having a pitch in the second direction generally equal to N.sub.2 .times.P.sub.1. In order to minimize the number of cell locations with respect to the wiring to which each cell is connected, the wires in the first array have offsets in the first direction which are a first function of their position in the second direction, and the wires in the second array have offsets in the second direction which are a second function of their position in the first direction.

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