Importance

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Abstract

A single chip integrated disc/servo controller and processor (CPU) for a disc drive reduces timing overhead associated with processor/controller/memory communication paths, increases speed, reduces the number of ASIC components, and increases reliability. The processor has a core that can be customized and implemented with appropriate hard disc drive specific controller technology including code or algorithms. Timing overhead associated with the conventional multi-chip communication paths is reduced by the inventive structure as the single on-chip processor has direct access to a buffer memory through a buffer manager within the controller logic. This eliminates the pin and pad delays that are present in conventional implementations. This performance increase has a direct positive impact on disc drive performance generally, and more particularly on disc drive performance when running code from the buffer memory. The structure and method also reduce overhead when communicating with the controller logic, and reduces the delays and other timing overhead associated with accesses to individual storage registers, which are generally slower in the conventional multi-chip configuration than in the single-chip integrated device. Single-chip integration also advantageously reduces product cost by removing one of the ASICs that would otherwise be required for the disc drive electronics. The single chip integration provided by the invention also advantageously includes structural features implemented in sub-micron semiconductor manufacturing technology to provide the aforementioned integration.

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First Claim